Products
ICube provides System-On-Chip (SOC) solutions based on the Harmony Unified Processor Technology. The Harmony Unified Processor Technology genuinely integrates two different processor types: a central processing unit (CPU) and a graphics processing unit (GPU), into one unified core. This technology consists of the Multi-Thread Virtual Pipeline parallel computing core (MVP), an independent instruction set architecture (ISA), an optimizing compiler and the Agile Switch dynamic load balancer.
ICube’s SOC solutions target devices in the hand-held computing and communication market, with a focus towards those based on the Android Operating System. ICube’s Harmony Unified Processor Technology results in superior price performance and power efficiency ratios in products incorporating the technology. This in turn reduces the device’s Bill of Materials without the need of any compromise in computing power or feature sets. Products that require computing cores such as embedded controllers, medical equipment, TV set-top boxes and home entertainment systems, all stand to benefit from ICube’s Harmony Unified Processor Technology.
ICube's IC1 Product Information
| CPU |
Dual-MVP
|
| GPU |
|
| System Clock | 600Mhz |
| Multi-thread Processing | Simultaneous 8 threads |
| Processing Power | 5160DMIPS, a peak performance similar to a 4.8GHz single serial core processor |
| Display System | LCD: Maximum pixel clock: 165MHz@16.7M (24-bit) true color, HDMI/DVI output capable |
| Camera | 8/10 bit camera data interface |
| Video | Support HD 720p H.264 decoding |
| Audio | Max. 5.1 channel audio |
| Memory | Support SD, HCSD, MMC card, USB mass storage device, Nand flash, NOR flash, DDR2 SDRAM |
| Power Control | 6 independent power domain, 3 low power modes |
| Supported OS | Android, Embedded Linux |
| Supported Connectivity | USB host/slave, WiFi, UART, 3G modem, GPS |
| Keypad | 12 keypad I/O for Qwerty keyboard |
MVP Core Technology Specifications
| A processor core based on parallel-computing with an integrated ISA |
| Up to 600 MHz. clock frequency on 65 nm process,4 threads |
| Super-scalar execution pipeline, offering sustainable performance of 2580 DMIPS (4.3 DMIPS/MHz) or 3.6 GFLOPS (6 MFLOPS/MHz.) |
| Up to 8 dynamically scheduled kernel instances with hardware load balancing and fine-grained simultaneous multithreading (SMT) |
| Data-parallel, task-parallel, and function-parallel computational models with minimum interrupts and context switches |
| 64KB I-Cache , 64KB D-Cache, 64KB SRAM and 32-bit GPR, 8-channel DMA and 16-source interrupt controller |
| Core area 3.0mm^2, including memory, with operating power of about 300mw |
| Support both homogeneous and heterogeneous parallel programming APIs through native compiler and MVP drivers |
